Hardware and Computer Organization

Contents
Preface to the First Edition .................................................................................. xi
Acknowledgments ............................................................................................. xvi
What’s on the DVD-ROM? ................................................................................ xvii
CHAPTER 1: Introduction and Overview of Hardware Architecture ................. 1
Introduction ................................................................................................................................ 1
A Brief History of Computing ...................................................................................................... 1
Number Systems ....................................................................................................................... 12
Converting Decimals to Bases .................................................................................................... 25
Engineering Notation ............................................................................................................... 26
Summary of Chapter 1 .............................................................................................................. 27
Exercises for Chapter 1 .............................................................................................................. 28
CHAPTER 2: Introduction to Digital Logic ......................................................... 29
Electronic Gate Description ........................................................................................................ 39
Truth Tables ............................................................................................................................... 44
Summary of Chapter 2 .............................................................................................................. 46
Exercises for Chapter 2 .............................................................................................................. 47
CHAPTER 3: Introduction to Asynchronous Logic ............................................. 49
Introduction .............................................................................................................................. 49
Laws of Boolean Algebra ........................................................................................................... 51
The Karnaugh Map ................................................................................................................... 55
Clocks and Pulses ...................................................................................................................... 62
Summary of Chapter 3 .............................................................................................................. 67
Exercises for Chapter 3 .............................................................................................................. 68
CHAPTER 4: Introduction to Synchronous Logic ............................................... 71
Flip-Flops ................................................................................................................................... 72
Storage Register ........................................................................................................................ 83
Summary of Chapter 4 .............................................................................................................. 90
Exercises for Chapter 4 .............................................................................................................. 91
CHAPTER 5: Introduction to State Machines ..................................................... 95
Modern Hardware Design Methodologies ................................................................................ 115
Summary of Chapter 5 ............................................................................................................ 119
Exercises for Chapter 5 ............................................................................................................ 120
CHAPTER 6: Bus Organization and Memory Design ....................................... 123
Bus Organization ..................................................................................................................... 123
Address Space ......................................................................................................................... 136
Direct Memory Access (DMA) .................................................................................................. 152
Summary of Chapter 6 ............................................................................................................ 153
Exercises for Chapter 6 ............................................................................................................ 155
CHAPTER 7: Memory Organization and Assembly Language Programming .. 159
Introduction ............................................................................................................................ 159
Label ....................................................................................................................................... 170
Effective Addresses .................................................................................................................. 174
Pseudo Opcodes ...................................................................................................................... 183
Data Storage Directives ............................................................................................................ 184
Analysis of an Assembly Language Program ............................................................................. 186
Summary of Chapter 7 ............................................................................................................ 188
Exercises for Chapter 7 ............................................................................................................ 189
CHAPTER 8: Programming in Assembly Language ......................................... 193
Introduction ............................................................................................................................ 193
Assembly Language and C++ .................................................................................................. 209
Stacks and Subroutines ........................................................................................................... 216
Summary of Chapter 8 ............................................................................................................ 222
Exercises for Chapter 8 ............................................................................................................ 223
CHAPTER 9: Advanced Assembly Language Programming Concepts ........... 229
Introduction ............................................................................................................................ 229
Advanced Addressing Modes ................................................................................................... 230
68000 Instructions .................................................................................................................. 232
MOVE Instructions ................................................................................................................... 233
Logical Instructions .................................................................................................................. 233
Other Logical Instructions ........................................................................................................ 234
Summary of the 68K Instructions ............................................................................................. 238
Simulated I/O Using the TRAP #15 Instruction ....................................................................... 240
Compilers and Assemblers ....................................................................................................... 242
Summary of Chapter 9 ............................................................................................................ 259
Exercises for Chapter 9 ............................................................................................................ 260
CHAPTER 10: The Intel x86 Architecture ......................................................... 265
Introduction ............................................................................................................................ 265
The Architecture of the 8086 CPU ........................................................................................... 267
Data, Index and Pointer Registers ............................................................................................ 269
Flag Registers .......................................................................................................................... 272
Segment Registers ................................................................................................................... 273
Instruction Pointer (IP) ............................................................................................................. 273
Memory Addressing Modes ..................................................................................................... 275
X86 Instruction Format ............................................................................................................ 278
8086 Instruction Set Summary ................................................................................................. 282
Data Transfer Instructions ........................................................................................................ 282
Arithmetic Instructions ............................................................................................................ 283
Logic Instructions .................................................................................................................... 284
String Manipulation ................................................................................................................. 285
Control Transfer ...................................................................................................................... 286
Assembly Language Programming the 8086 Architecture ....................................................... 289
System Vectors ........................................................................................................................ 291
System Startup ........................................................................................................................ 292
Wrap-Up ................................................................................................................................. 292
Summary of Chapter 10 .......................................................................................................... 292
Exercises for Chapter 10 .......................................................................................................... 294
CHAPTER 11: The ARM Architecture ................................................................ 295
Introduction ............................................................................................................................ 295
ARM Architecture .................................................................................................................... 296
Conditional Execution ............................................................................................................ 301
Barrel Shifter ........................................................................................................................... 302
Operand Size ........................................................................................................................... 303
Addressing Modes ................................................................................................................... 304
Stack Operations ..................................................................................................................... 306
ARM Instruction Set ................................................................................................................ 309
ARM System Vectors ............................................................................................................... 319
Summary and Conclusions ...................................................................................................... 320
Summary of Chapter 11 .......................................................................................................... 320
Exercises for Chapter 11 .......................................................................................................... 321
CHAPTER 12: Interfacing with the Real World ................................................ 322
Introduction ............................................................................................................................ 322
Interrupts ................................................................................................................................ 323
Exceptions ............................................................................................................................... 327
Motorola 68K Interrupts .......................................................................................................... 327
Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Conversion ............................................... 332
The Resolution of A/D and D/A Converters .............................................................................. 346
Summary of Chapter 12 .......................................................................................................... 348
Exercises for Chapter 12 .......................................................................................................... 349
CHAPTER 13: Introduction to Modern Computer Architectures .................... 353
Processor Architectures, CISC, RISC and DSP ........................................................................... 354
An Overview of Pipelining ....................................................................................................... 358
Summary of Chapter 13 .......................................................................................................... 369
Exercises for Chapter 13 .......................................................................................................... 370
CHAPTER 14: Memory Revisited, Caches and Virtual Memory ...................... 372
Introduction to Caches ............................................................................................................ 372
Virtual Memory ....................................................................................................................... 387
Pages ...................................................................................................................................... 389
Translation Lookaside Buffer (TLB) ............................................................................................ 391
Protection ................................................................................................................................ 392
Summary of Chapter 14 .......................................................................................................... 393
Exercises for Chapter 14 .......................................................................................................... 395
CHAPTER 15: Performance Issues in Computer Architecture ......................... 397
Introduction ............................................................................................................................ 397
Hardware and Performance ..................................................................................................... 398
Best Practices .......................................................................................................................... 414
Summary of Chapter 15 .......................................................................................................... 416
Exercises for Chapter 15 .......................................................................................................... 417
CHAPTER 16: Future Trends and Reconfigurable Hardware .......................... 419
Introduction ............................................................................................................................ 419
Reconfigurable Hardware ........................................................................................................ 419
Molecular Computing ............................................................................................................. 430
Local clocks ............................................................................................................................. 432
Summary of Chapter 16 .......................................................................................................... 434
Exercises for Chapter 16 .......................................................................................................... 436
APPENDIX A: Solutions for Odd-Numbered Exercises ................................... 437
[Solutions to the even-numbered problems are available through the instructor’s resource website at http://www.elsevier.com/0750678860.]
About the Author ............................................................................................. 483
Index .................................................................................................................. 485

Other Hardware Books
Other Core of CS Books
Computer Organization and Architecture 6th Edition
Fundamentals Of Computer Organization And Architecture
Computer Organization
Computer organization Notes
Download

Fundamentals Of Logic Design 5 Ed Instructor Manual

Charles Roth - Solutions Manual

TABLE OF CONTENTS
I. INTRODUCTION
1.1 Using the Text in a Lecture Course
1.2 Some Remarks About the Text
1.3 Using the Text in a Self-Paced Course
1.4 Use of Computer Software
1.5 Suggested Equipment for Laboratory Exercises
II. SOLUTIONS TO HOMEWORK PROBLEMS
Unit 1 Solutions 5
Unit 2 Solutions 11
Unit 3 Solutions 16
Unit 4 Solutions 21
Unit 5 Solutions 27
Unit 6 Solutions 37
Unit 7 Solutions 46
Unit 8 Solutions 63
Unit 9 Solutions 65
Unit 10 Solutions 76
Unit 11 Solutions 78
Unit 12 Solutions 81
Unit 13 Solutions 91
Unit 14 Solutions 99
Unit 15 Solutions 113
Unit 16 Solutions 131
Unit 17 Solutions 136
Unit 18 Solutions 141
Unit 19 Solutions 150
Unit 20 Solutions 156
III. SOLUTIONS TO DESIGN, SIMULATION, AND LAB EXERCISES
Unit 8 Design Problems 158
Unit 10 Design and Simulation Problems 177
Unit 12 Design and Simulation Problems 191
Unit 16 Design and Simulation Problems 196
Unit 17 Simulation and Lab Problems 205
Unit 20 Lab Design Problems 213
IV. SAMPLE UNIT TESTS 225


Logic synthesis - Wikipedia, the free encyclopedia
logic design (computer technology) -- Britannica Online Encyclopedia
Handbook of Logic in Computer Science Volume 5 Logic and Algebraic Methods
Finite Automata, Formal Logic, and Circuit Complexity
Other Hardware Books
Download

Digital Logic And Microprocessor Design With Vhdl

Enoch O. Hwang
La Sierra University, Riverside

Contents ....................................................................................................................................................................
Preface ...................................................................................................................................................................
Chapter 1 Designing Microprocessors......................................................................................
1.1 Overview of a Microprocessor .......................................................................................................................
1.2 Design Abstraction Levels..............................................................................................................................
1.3 Examples of a 2-to-1 Multiplexer ...................................................................................................................
1.3.1 Behavioral Level....................................................................................................................................
1.3.2 Gate Level..............................................................................................................................................
1.3.3 Transistor Level .....................................................................................................................................
1.4 Introduction to VHDL ....................................................................................................................................
1.5 Synthesis.......................................................................................................................................................
1.6 Going Forward..............................................................................................................................................
1.7 Summary Checklist.......................................................................................................................................
1.8 Problems .......................................................................................................................................................

Chapter 2 Digital Circuits.......................................................................................................... 2
2.1 Binary Numbers.............................................................................................................................................. 3
2.2 Binary Switch .................................................................................................................................................
2.3 Basic Logic Operators and Logic Expressions ...............................................................................................
2.4 Truth Tables....................................................................................................................................................
2.5 Boolean Algebra and Boolean Function .........................................................................................................
2.5.1 Boolean Algebra ....................................................................................................................................
2.5.2 * Duality Principle...............................................................................................................................
2.5.3 Boolean Function and the Inverse........................................................................................................
2.6 Minterms and Maxterms...............................................................................................................................
2.6.1 Minterms..............................................................................................................................................
2.6.2 * Maxterms ..........................................................................................................................................
2.7 Canonical, Standard, and non-Standard Forms.............................................................................................
2.8 Logic Gates and Circuit Diagrams................................................................................................................
2.9 Example: Designing a Car Security System .................................................................................................
2.10 VHDL for Digital Circuits............................................................................................................................
2.10.1 VHDL code for a 2-input NAND gate.................................................................................................
2.10.2 VHDL code for a 3-input NOR gate....................................................................................................
2.10.3 VHDL code for a function ...................................................................................................................
2.11 Summary Checklist.......................................................................................................................................
2.12 Problems .......................................................................................................................................................

Chapter 3 Combinational Circuits............................................................................................
3.1 Analysis of Combinational Circuits................................................................................................................
3.1.1 Using a Truth Table ...............................................................................................................................
3.1.2 Using a Boolean Function......................................................................................................................
3.2 Synthesis of Combinational Circuits ..............................................................................................................
3.3 * Technology Mapping...................................................................................................................................
3.4 Minimization of Combinational Circuits ......................................................................................................
3.4.1 Karnaugh Maps....................................................................................................................................
3.4.2 Don’t-cares ..........................................................................................................................................
3.4.3 * Tabulation Method............................................................................................................................
3.5 * Timing Hazards and Glitches ....................................................................................................................
3.5.1 Using Glitches .....................................................................................................................................
3.6 BCD to 7-Segment Decoder .........................................................................................................................
3.7 VHDL for Combinational Circuits ...............................................................................................................
3.7.1 Structural BCD to 7-Segment Decoder................................................................................................
3.7.2 Dataflow BCD to 7-Segment Decoder ................................................................................................
3.7.3 Behavioral BCD to 7-Segment Decoder..............................................................................................
3.8 Summary Checklist.......................................................................................................................................
3.9 Problems .......................................................................................................................................................

Chapter 4 Standard Combinational Components...................................................................
4.1 Signal Naming Conventions ...........................................................................................................................
4.2 Adder ..............................................................................................................................................................
4.2.1 Full Adder..............................................................................................................................................
4.2.2 Ripple-carry Adder ................................................................................................................................
4.2.3 * Carry-lookahead Adder.......................................................................................................................
4.3 Two’s Complement Binary Numbers .............................................................................................................
4.4 Subtractor........................................................................................................................................................
4.5 Adder-Subtractor Combination.....................................................................................................................
4.6 Arithmetic Logic Unit...................................................................................................................................
4.7 Decoder.........................................................................................................................................................
4.8 Encoder.........................................................................................................................................................
4.8.1 * Priority Encoder................................................................................................................................
4.9 Multiplexer ...................................................................................................................................................
4.9.1 * Using Multiplexers to Implement a Function ...................................................................................
4.10 Tri-state Buffer .............................................................................................................................................
4.11 Comparator ...................................................................................................................................................
4.12 Shifter ...........................................................................................................................................................
4.12.1 * Barrel Shifter ....................................................................................................................................
4.13 * Multiplier ...................................................................................................................................................
4.14 Summary Checklist.......................................................................................................................................
4.15 Problems .......................................................................................................................................................

Chapter 5 * Implementation Technologies .............................................................................
5.1 Physical Abstraction .......................................................................................................................................
5.2 Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)..................................................................
5.3 CMOS Logic...................................................................................................................................................
5.4 CMOS Circuits ...............................................................................................................................................
5.4.1 CMOS Inverter ......................................................................................................................................
5.4.2 CMOS NAND gate................................................................................................................................
5.4.3 CMOS AND gate...................................................................................................................................
5.4.4 CMOS NOR and OR Gates ................................................................................................................ 1
5.4.5 Transmission Gate ...............................................................................................................................
5.4.6 2-input Multiplexer CMOS Circuit..................................................................................................... 1
5.4.7 CMOS XOR and XNOR Gates............................................................................................................ 1
5.5 Analysis of CMOS Circuits ......................................................................................................................... . 1
5.6 Using ROMs to Implement a Function........................................................................................................ . 15
5.7 Using PLAs to Implement a Function .......................................................................................................... 1
5.8 Using PALs to Implement a Function .......................................................................................................... 1
5.9 Complex Programmable Logic Device (CPLD) ...........................................................................................
5.10 Field Programmable Gate Array (FPGA) .....................................................................................................
5.11 Summary Checklist.......................................................................................................................................
5.12 Problems .......................................................................................................................................................
Chapter 6 Latches and Flip-Flops ............................................................................................
6.1 Bistable Element.............................................................................................................................................
6.2 SR Latch .........................................................................................................................................................
6.3 SR Latch with Enable .....................................................................................................................................
6.4 D Latch ...........................................................................................................................................................
6.5 D Latch with Enable .......................................................................................................................................
6.6 Clock...............................................................................................................................................................
6.7 D Flip-Flop .................................................................................................................................................. . 1
6.7.1 * Alternative Smaller Circuit............................................................................................................... 1
6.8 D Flip-Flop with Enable ............................................................................................................................... 1
6.9 Asynchronous Inputs .................................................................................................................................... 1
6.10 Description of a Flip-Flop ............................................................................................................................
6.10.1 Characteristic Table ............................................................................................................................. 1
6.10.2 Characteristic Equation........................................................................................................................ 1
6.10.3 State Diagram ...................................................................................................................................... 1
6.10.4 Excitation Table................................................................................................................................... 1
6.11 Timing Issues................................................................................................................................................ 1
6.12 Example: Car Security System – Version 2..................................................................................................
6.13 VHDL for Latches and Flip-Flops................................................................................................................ 1
6.13.1 Implied Memory Element.................................................................................................................... 1
6.13.2 VHDL Code for a D Latch with Enable ..............................................................................................
6.13.3 VHDL Code for a D Flip-Flop ........................................................................................................... . 19
6.13.4 VHDL Code for a D Flip-Flop with Enable and Asynchronous Set and Clear ...................................
6.14 * Flip-Flop Types .........................................................................................................................................
6.14.1 SR Flip-Flop ........................................................................................................................................
6.14.2 JK Flip-Flop.........................................................................................................................................
6.14.3 T Flip-Flop...........................................................................................................................................
6.15 Summary Checklist.......................................................................................................................................
6.16 Problems .......................................................................................................................................................

Chapter 7 Sequential Circuits ................................................................................................... 2
7.1 Finite-State-Machine (FSM) Models..............................................................................................................
7.2 State Diagrams................................................................................................................................................
7.3 Analysis of Sequential Circuits.......................................................................................................................
7.3.1 Excitation Equation ...............................................................................................................................
7.3.2 Next-state Equation ...............................................................................................................................
7.3.3 Next-state Table.....................................................................................................................................
7.3.4 Output Equation...................................................................................................................................
7.3.5 Output Table ........................................................................................................................................
7.3.6 State Diagram ..................................................................................................................................... . 0
7.3.7 Example: Analysis of a Moore FSM ...................................................................................................
7.3.8 Example: Analysis of a Mealy FSM....................................................................................................
7.4 Synthesis of Sequential Circuits ...................................................................................................................
7.4.1 State Diagram ......................................................................................................................................
7.4.2 Next-state Table...................................................................................................................................
7.4.3 Implementation Table..........................................................................................................................
7.4.4 Excitation Equation and Next-state Circuit .........................................................................................
7.4.5 Output Table and Equation ................................................................................................................. . 1
7.4.6 FSM Circuit .........................................................................................................................................
7.4.7 Examples: Synthesis of Moore FSMs..................................................................................................
7.4.8 Example: Synthesis of a Mealy FSM...................................................................................................
7.5 Unused State Encodings and the Encoding of States....................................................................................
7.6 Example: Car Security System – Version 3..................................................................................................
7.7 VHDL for Sequential Circuits ......................................................................................................................
7.8 * Optimization for Sequential Circuits .........................................................................................................
7.8.1 State Reduction................................................................................................................................... . 3
7.8.2 State Encoding .....................................................................................................................................
7.8.3 Choice of Flip-Flops ............................................................................................................................
7.9 Summary Checklist.......................................................................................................................................
7.10 Problems .......................................................................................................................................................

Chapter 8 Standard Sequential Components .......................................................................... 2
8.1 Registers .........................................................................................................................................................
8.2 Shift Registers.................................................................................................................................................
8.2.1 Serial-to-Parallel Shift Register .............................................................................................................
8.2.2 Serial-to-Parallel and Parallel-to-Serial Shift Register ..........................................................................
8.3 Counters..........................................................................................................................................................
8.3.1 Binary Up Counter.................................................................................................................................
8.3.2 Binary Up-Down Counter....................................................................................................................
8.3.3 Binary Up-Down Counter with Parallel Load .....................................................................................
8.3.4 BCD Up Counter .................................................................................................................................
8.3.5 BCD Up-Down Counter ......................................................................................................................
8.4 Register Files ................................................................................................................................................
8.5 Static Random Access Memory.................................................................................................................... 2
8.6 * Larger Memories .......................................................................................................................................
8.6.1 More Memory Locations ..................................................................................................................... 2
8.6.2 Wider Bit Width .................................................................................................................................. 2
8.7 Summary Checklist....................................................................................................................................... 2
8.8 Problems ....................................................................................................................................................... 2

Chapter 9 Datapaths .................................................................................................................. 2
9.1 Designing Dedicated Datapaths......................................................................................................................
9.1.1 Selecting Registers.................................................................................................................................
9.1.2 Selecting Functional Units.....................................................................................................................
9.1.3 Data Transfer Methods ..........................................................................................................................
9.1.4 Generating Status Signals ....................................................................................................................
9.2 Using Dedicated Datapaths...........................................................................................................................
9.3 Examples of Dedicated Datapaths ................................................................................................................
9.3.1 Simple IF-THEN-ELSE.......................................................................................................................
9.3.2 Counting 1 to 10 ..................................................................................................................................
9.3.3 Summation of n down to 1...................................................................................................................
9.3.4 Factorial ...............................................................................................................................................
9.3.5 Count Zero-One ...................................................................................................................................
9.4 General Datapaths.........................................................................................................................................
9.5 Using General Datapaths ..............................................................................................................................
9.6 A More Complex General Datapath .............................................................................................................
9.7 Timing Issues................................................................................................................................................
9.8 VHDL for Datapaths.....................................................................................................................................
9.8.1 Dedicated Datapath..............................................................................................................................
9.8.2 General Datapath .................................................................................................................................
9.9 Summary Checklist.......................................................................................................................................
9.10 Problems .......................................................................................................................................................

Chapter 10 Control Units ............................................................................................................
10.1 Constructing the Control Unit.........................................................................................................................
10.2 Examples ........................................................................................................................................................
10.2.1 Count 1 to 10 .........................................................................................................................................
10.2.2 Summation of 1 to n ..............................................................................................................................
10.3 Generating Status Signals .............................................................................................................................
10.4 Timing Issues................................................................................................................................................
10.5 Standalone Controllers..................................................................................................................................
10.5.1 Rotating Lights ....................................................................................................................................
10.5.2 PS/2 Keyboard Controller....................................................................................................................
10.5.3 VGA Monitor Controller ..................................................................................................................... 6
10.6 * ASM Charts and State Action Tables ....................................................................................................... . 3 7
10.6.1 ASM Charts ........................................................................................................................................ 3 7
10.6.2 State Action Tables.............................................................................................................................. 0
10.7 VHDL for Control Units............................................................................................................................... 1
10.8 Summary Checklist....................................................................................................................................... 2
10.9 Problems ....................................................................................................................................................... 4

Chapter 11 Dedicated Microprocessors .....................................................................................
11.1 Manual Construction of a Dedicated Microprocessor ....................................................................................
11.2 Examples ........................................................................................................................................................
11.2.1 Greatest Common Divisor .....................................................................................................................
11.2.2 Summing Input Numbers.....................................................................................................................
11.2.3 High-Low Guessing Game ..................................................................................................................
11.2.4 Finding Largest Number......................................................................................................................
11.3 VHDL for Dedicated Microprocessors.........................................................................................................
11.3.1 FSM + D Model...................................................................................................................................
11.3.2 FSMD Model.......................................................................................................................................
11.3.3 Behavioral Model ................................................................................................................................
11.4 Summary Checklist.......................................................................................................................................
11.5 Problems .......................................................................................................................................................

Chapter 12 General-Purpose Microprocessors .........................................................................
12.1 Overview of the CPU Design .........................................................................................................................
12.2 The EC-1 General-Purpose Microprocessor...................................................................................................
12.2.1 Instruction Set........................................................................................................................................
12.2.2 Datapath................................................................................................................................................. 5
12.2.3 Control Unit...........................................................................................................................................
12.2.4 Complete Circuit....................................................................................................................................
12.2.5 Sample Program................................................................................................................................... 0
12.2.6 Simulation............................................................................................................................................
12.2.7 Hardware Implementation ................................................................................................................... 2
12.3 The EC-2 General-Purpose Microprocessor................................................................................................. 3
12.3.1 Instruction Set......................................................................................................................................
12.3.2 Datapath............................................................................................................................................... 4
12.3.3 Control Unit......................................................................................................................................... 5
12.3.4 Complete Circuit.................................................................................................................................. 8
12.3.5 Sample Program................................................................................................................................... 9
12.3.6 Hardware Implementation ................................................................................................................... 1
12.4 VHDL for General-Purpose Microprocessors .............................................................................................. 2
12.4.1 Structural FSM+D ............................................................................................................................... 2
12.4.2 Behavioral FSMD................................................................................................................................ 9
12.5 Summary Checklist....................................................................................................................................... 2
12.6 Problems ....................................................................................................................................................... 2

Appendix A Schematic Entry Tutorial 1 ....................................................................................
A.1 Getting Started ................................................................................................................................................
A.1.1 Preparing a Folder for the Project..........................................................................................................
A.1.2 Starting MAX+plus II............................................................................................................................
A.1.3 Starting the Graphic Editor ....................................................................................................................
A.2 Using the Graphic Editor ................................................................................................................................ 4
A.2.1 Drawing Tools ....................................................................................................................................... 4
A.2.2 Inserting Logic Symbols........................................................................................................................ 4
A.2.3 Selecting, Moving, Copying, and Deleting Logic Symbols...................................................................
A.2.4 Making and Naming Connections ......................................................................................................... 6
A.2.5 Selecting, Moving and Deleting Connection Lines ...............................................................................
A.3 Specifying the Top-Level File and Project .....................................................................................................
A.3.1 Saving the Schematic Drawing..............................................................................................................
A.3.2 Specifying the Project............................................................................................................................
A.4 Synthesis for Functional Simulation...............................................................................................................
A.5 Circuit Simulation...........................................................................................................................................
A.5.1 Selecting Input Test Signals ..................................................................................................................
A.5.2 Customizing the Waveform Editor ......................................................................................................
A.5.3 Assigning Values to the Input Signals .................................................................................................
A.5.4 Saving the Waveform File ...................................................................................................................
A.5.5 Starting the Simulator ..........................................................................................................................
A.6 Creating and Using the Logic Symbol..........................................................................................................

Appendix B VHDL Entry Tutorial 2...........................................................................................
B.1 Getting Started ................................................................................................................................................
B.1.1 Preparing a Folder for the Project..........................................................................................................
B.1.2 Starting MAX+plus II............................................................................................................................
B.1.3 Creating a Project ..................................................................................................................................
B.1.4 Editing the VHDL Source Code ............................................................................................................
B.2 Synthesis for Functional Simulation...............................................................................................................
B.3 Circuit Simulation...........................................................................................................................................
B.3.1 Selecting Input Test Signals ..................................................................................................................
B.3.2 Customizing the Waveform Editor ........................................................................................................
B.3.3 Assigning Values to the Input Signals ...................................................................................................
B.3.4 Saving the Waveform File .....................................................................................................................
B.3.5 Starting the Simulator ............................................................................................................................

Appendix C UP2 Programming Tutorial 3.................................................................................
C.1 Getting Started ................................................................................................................................................
C.1.1 Preparing a Folder for the Project..........................................................................................................
C.1.2 Creating a Project ..................................................................................................................................
C.1.3 Viewing the Source File ........................................................................................................................
C.2 Synthesis for Programming the PLD ..............................................................................................................
C.3 Circuit Simulation...........................................................................................................................................
C.4 Using the Floorplan Editor .............................................................................................................................
C.4.1 Selecting the Target Device...................................................................................................................
C.4.2 Maping the I/O Pins with the Floorplan Editor......................................................................................
C.5 Fitting the Netlist and Pins to the PLD ...........................................................................................................
C.6 Hardware Setup ............................................................................................................................................
C.6.1 Installing the ByteBlaster Driver .........................................................................................................
C.6.2 Jumper Settings....................................................................................................................................
C.6.3 Hardware Connections........................................................................................................................
C.7 Programming the PLD..................................................................................................................................
C.8 Testing the Hardware....................................................................................................................................
C.9 MAX7000S EPM7128SLC84-7 Summary...................................................................................................
C.9.1 JTAG Jumper Settings .........................................................................................................................
C.9.2 Prototyping Resources for Use ............................................................................................................
C.9.3 General Pin Assignments.....................................................................................................................
C.9.4 Two Pushbutton Switches....................................................................................................................
C.9.5 16 DIP Switches ..................................................................................................................................
C.9.6 16 LEDs...............................................................................................................................................
C.9.7 7-Segment LEDs..................................................................................................................................
C.9.8 Clock....................................................................................................................................................
C.10 FLEX10K EPF10K70RC240-4 Summary....................................................................................................
C.10.1 JTAG Jumper Settings .........................................................................................................................
C.10.2 Prototyping Resources for Use ............................................................................................................
C.10.3 Two Pushbutton Switches....................................................................................................................
C.10.4 8 DIP Switches ....................................................................................................................................
C.10.5 7-Segment LEDs..................................................................................................................................
C.10.6 Clock....................................................................................................................................................
C.10.7 PS/2 Port..............................................................................................................................................
C.10.8 VGA Port.............................................................................................................................................

Appendix D VHDL Summary......................................................................................................
D.1 Basic Language Elements...............................................................................................................................
D.1.1 Comments..............................................................................................................................................
D.1.2 Identifiers...............................................................................................................................................
D.1.3 Data Objects ..........................................................................................................................................
D.1.4 Data Types.............................................................................................................................................
D.1.5 Data Operators.......................................................................................................................................
D.1.6 ENTITY.................................................................................................................................................
D.1.7 ARCHITECTURE.................................................................................................................................
D.1.8 GENERIC..............................................................................................................................................
D.1.9 PACKAGE ............................................................................................................................................
D.2 Dataflow Model Concurrent Statements.......................................................................................................
D.2.1 Concurrent Signal Assignment ............................................................................................................ 0
D.2.2 Conditional Signal Assignment ...........................................................................................................
D.2.3 Selected Signal Assignment.................................................................................................................
D.2.4 Dataflow Model Example.................................................................................................................... 2
D.3 Behavioral Model Sequential Statements .....................................................................................................
D.3.1 PROCESS............................................................................................................................................
D.3.2 Sequential Signal Assignment .............................................................................................................
D.3.3 Variable Assignment ...........................................................................................................................
D.3.4 WAIT...................................................................................................................................................
D.3.5 IF THEN ELSE....................................................................................................................................
D.3.6 CASE ................................................................................................................................................... 4
D.3.7 NULL...................................................................................................................................................
D.3.8 FOR .....................................................................................................................................................
D.3.9 WHILE ................................................................................................................................................
D.3.10 LOOP...................................................................................................................................................
D.3.11 EXIT ....................................................................................................................................................
D.3.12 NEXT...................................................................................................................................................
D.3.13 FUNCTION .........................................................................................................................................
D.3.14 PROCEDURE......................................................................................................................................
D.3.15 Behavioral Model Example .................................................................................................................
D.4 Structural Model Statements.........................................................................................................................
D.4.1 COMPONENT Declaration.................................................................................................................
D.4.2 PORT MAP .........................................................................................................................................
D.4.3 OPEN...................................................................................................................................................
D.4.4 GENERATE ........................................................................................................................................
D.4.5 Structural Model Example ...................................................................................................................
D.5 Conversion Routines..................................................................................................................................... 1
D.5.1 CONV_INTEGER() ............................................................................................................................ 1
D.5.2 CONV_STD_LOGIC_VECTOR(,).....................................................................................................


Hardware - Wikipedia, the free encyclopedia, Tom's Hardware: Hardware News, Tests and Reviews, Computer Hardware, Restoration Hardware, Hardware Store, Home Hardware, What is Hardware

UML Xtra-Light: How to Specify Your Hardware Requirements
Universal Serial Bus System Architecture (USB 2.0)
Other Hardware Books
Download

µC/OS-II, The Real-Time Kernel

Chapter contents:

Chapter 1, Sample Code
This chapter is designed to allow you to quickly experiment with and use µC/OS-II. The chapter starts by showing
you how to install the distribution diskette and describe the directories created. I then explain some of the coding
conventions used. Before getting into the description of the examples, I describe the code used to access some of the
services provided on a PC.

Chapter 2, Real-Time Systems Concepts
Here, I introduce you to some real-time systems concepts such as foreground/background systems, critical sections,
resources, multitasking, context switching, scheduling, reentrancy, task priorities, mutual exclusion, semaphores,
intertask communications, interrupts and more.

Chapter 3, Kernel Structure
This chapter introduces you to µC/OS-II and its internal structure. You will learn about tasks, task states, task control
blocks, how µC/OS-II implements a ready list, task scheduling, the idle task, how to determine CPU usage, how
µC/OS-II handles interrupts, how to initialize and start µC/OS-II and more.

Chapter 4, Task Management
This chapter describes µC/OS-II’s services to create a task, delete a task, check the size of a task’s stack, change a
task’s priority, suspend and resume a task, and get information about a task.

Chapter 5, Time Management
This chapter describes how µC/OS-II can suspend a task’s execution until some user specified time expires, how such
a task can be resumed and how to get and set the current value of a 32-bit tick counter.

Chapter 6, Intertask Communication and Synchronization
This chapter describes µC/OS-II’s services to have tasks and ISRs (Interrupt Service Routines) communicate with one
another and share resources. You will learn how sempahores, message mailboxes and message queues are
implemented.

Chapter 7, Memory Management
This chapter describes µC/OS-II’s dynamic memory allocation feature using fixed-sized memory blocks.

Chapter 8, Porting µC/OS-II
This chapter describes in general terms what needs to be done to adapt µC/OS-II to different processor architectures.


Chapter 9, 80x86 Large Model Port
This chapter describes how µC/OS-II was ported to the Intel/AMD 80x86 processor architecture running in real-mode
and for the large model. Code and data space memory usage is provided as well as execution times for each of the
functions.

Chapter 10, Upgrading from µC/OS to µC/OS-II
This chapter describes how easy it is to migrate a port done for µC/OS to work with µC/OS-II.

Chapter 11, Reference Manual
This chapter describes each of the functions (i.e. services) provided by µC/OS-II from an application developer’s
standpoint. Each function contains a brief description, its prototype, the name of the file where the function is found,
a description of the function arguments and the return value, special notes and examples.

Chapter 12, Configuration Manual
This chapter describes each of the #define constants used to configure µC/OS-II for your application. Configuring
µC/OS-II allows you to use only the services required by your application. This gives you the flexibility to reduce
µC/OS-II’s memory footprint (code and data space).

Appendix A, Example Source Code
Fully commented source code for the examples and PC services (see Chapter 1) is provided in this appendix and
consist of 11 files.

Appendix B, µC/OS-II Microprocessor Independent Source Code
The source code for the portion of µC/OS-II that is not dependent on any specific processor is provided in this
appendix and consist of 9 files

Appendix C, 80x86 Real-Mode, Large Model Source Code
The source code for the 80x86 processor dependent functions is found in this appendix and consist of three files.

Appendix D, TO and HPLISTC
Presents two DOS utilities that I use: TO and HPLISTC. TO is a utility that I use to quickly move between MS-DOS
directories without having to type the CD (change directory) command. HPLISTC is a utility to print C source code in
compressed mode (i.e. 17 CPI) and allows you to specify page breaks. The printout is assumed to be to a Hewlett
Packard (HP) Laserjet type printer.

Appendix E, Bibliography
This section provides a bibliography of reference material that you may find useful if you are interested in getting
further information about embedded real-time systems.

Appendix F, Licensing
Describes the licensing policy for distributing µC/OS-II in source and object form.

Another Hardware Books
Download

Application-Specific Integrated Circuits

Michael John Sebastian Smith
Addison-Wesley
VLSI Systems Series
1,040 pages
ISBN: 0-201-50022-1
June 1997

Table of Contents

Preface
Chapter 1: Introduction to ASICs
Chapter 2: CMOS Logic
Chapter 3: ASIC Library Design
Chapter 4: Programmable ASICs
Chapter 5: Programmable ASIC Logic Cells
Chapter 6: Programmable ASIC I/O Cells
Chapter 7: Programmable ASIC Interconnect
Chapter 8: Programmable ASIC Design Software
Chapter 9: Low-Level Design Entry
Chapter 10: VHDL
Chapter 11: Verilog HDL
Chapter 12: Logic Synthesis
Chapter 13: Simulation
Chapter 14: Test
Chapter 15: System Partitioning
Chapter 16: Floorplanning and Placement
Chapter 17: Routing
Appendix A: VHDL Resources
Appendix B: Verilog HDL Resources


Another Hardware Books
Another Electronic Books
Download
Download

ARM Architecture Reference Manual

Publisher: Addison-Wesley Professional; 2 edition | ISBN : 0201737191 | January 6, 2001 | 811 pages | PDF | 12.7MB

“Covers everything you might need to know about ARM assembly language programming. It has three sections: A. CPU Architecture - ARM instruction set (regular and Thumb) - ARM addressing modes - Examples B. Memory and System Architecture -System Control Coprocessor, MMU, Protection Unit, Caches and Write Buffers C. Vector Floating Point Architecture - Formats, instructions and addressing modes. If you work with an ARM processor of any type, you simply must have this book. It is *the* reference, -- the best source of exact instruction details, as well as memory management unit details. If you're writing code for the ARM, you need this one.”



Another Hardware Books
Download

Embedded Control Systems in C/C++: An Introduction for Software Developers Using MATLAB

by Jim Ledin ISBN:1578201276
CMP Books © 2004 (252 pages)
The author of this text illustrates how to implement control systems in your resource-limited embedded systems. Using C or C++, you will learn to design and test control systems to ensure a high level of performance and robustness.

CD Content




Table of Contents
Embedded Control Systems in C/C++—An Introduction for Software Developers Using MATLAB
Preface
Chapter 1 - Control Systems Basics
Chapter 2 - PID Control
Chapter 3 - Plant Models
Chapter 4 - Classical Control System Design
Chapter 5 - Pole Placement
Chapter 6 - Optimal Control
Chapter 7 - MIMO Systems
Chapter 8 - Discrete-Time Systems and Fixed-Point Mathematics
Chapter 9 - Control System Integration and Testing
Chapter 10 - Wrap-Up and Design Example
Glossary
Index
List of Figures
List of Tables
List of Advanced Concepts
List of Sidebars


Another C++ Books
Another C Books
Another Hardware Books
Download